As technology scales down in size, delay defects are becoming more significant. Crosstalk-aggravated delay defects can be introduced by long parallel nets. The long parallel nets provide a substantial platform for electrical coupling from multiple “aggressors” (nets from which capacitive coupling and/or mutual inductance originates) to the path of a “victim” (a net that receives the capacitive coupling and/or mutual inductance). As processing speeds increase and operating voltages decrease with the scaling of technology, conventional fault models and ATPG (automated test program generation) tools do not adequately test for accumulative crosstalk along a path or provide a method for detecting such faults during silicon validation and testing for manufacturing defects.